What you will be doing:
Methodology Deployment: Design and refine sophisticated Synthesis flows to meet ambitious Power, Performance, and Area (PPA) objectives.
Partner closely with upstream Front-End Design and downstream Place & Route (P&R) flows development teams. Define boundaries, resolve design constraints, and bridge systemic execution gaps.
Develop robust and scalable scripts using Tcl/Python to improve Flow Turnaround Time (TAT). Integrate next-generation capabilities such as AI/ML automation into production runs.
Serve as a subject matter expert and trusted representative for adjacent project teams. Provide proactive support, deep-dive debugging of complex tool failures, and formal synthesis training to build teams.
What we need to see:
Academic Background: B.Sc./M.Sc. in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience.
Core Synthesis Experience: 3+ years of hands-on experience in VLSI synthesis flows, with deep, proven expertise in Synopsys Fusion Compiler or Design Compiler (DC-Top/DC-Ultra).
Technical Skills: Strong proficiency in Tcl or Python scripting within a production-level CAD/EDA environment.
Attitude & Ownership: A highly enthusiastic, dedicated approach with a demonstrated "sense of ownership" to proactively step into process vacuums and drive complex tasks to completion.
Ways to stand out from the crowd:
Familiarity with synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Genus/ Innovus/Tempus).
Experience in methodology definition / flow ownership of synthesis / Place and Route/ STA steps is an advantage.
Great teammate with strong ownership, self-learning skills, and the ability to work autonomously.
