What you'll be doing:
Perform advanced Static Timing Analysis (STA) for HSIO at chiplet and FC level.
Running Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages.
Responsible for a full timing closer and quality approval from pre-layout STA model through signoff.
AI use for timing optimization and data analysis.
What we need to see:
B.SC./ M.SC. in Electrical Engineering.
At least 5+ years of hands-on STA experience.
Experience in Prime Time and signoff methodologies.
A great teammate who thrives in a collaborative environment.
AI tools orientation or alternatively a desire to learn.
Ways to stand out from the crowd:
Agentic Frameworks.
AI prompting experience.
Experience in Linux environments.
TCL, Python, shell scripting abilities.
Experience with data collection and analysis.
