We are in the early stages of a new project and looking for a talented Senior engineer to take on a key role, leading Verification efforts of major parts of our ASIC – from scratch
Roles and responsibilities:
Take ownership of Verification for large ASIC clusters.
Plan, build, and execute the Verification environment end-to-end.
Mentor and guide juniors/students.
Roles and responsibilities:
Take ownership of Verification for large ASIC clusters.
Plan, build, and execute the Verification environment end-to-end.
Mentor and guide juniors/students.
Requirements:
B.Sc. in Electrical Engineering or a related field.
6+ years of experience in ASIC/SoC Verification.
Experience leading verification planning and execution independently.
Preferred:
Familiarity with RDMA, Ethernet, DDR or RISC-V.
B.Sc. in Electrical Engineering or a related field.
6+ years of experience in ASIC/SoC Verification.
Experience leading verification planning and execution independently.
Preferred:
Familiarity with RDMA, Ethernet, DDR or RISC-V.
This position is open to all candidates.
