As a Silicon Validation/Emulation Design Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators, as well as multiple ARM-based sub-systems. You will be a key contributor in our pre-silicon hardware validation efforts using Cadence Palladium emulation platforms, enabling early system integration and hardware validation. You will work closely with SoC architects, RTL designers, and verification engineers to ensure our designs are thoroughly validated before tape-out. You will help define the processes, methods, and tools for emulation environment development and debug of large complex SoCs.
If you enjoy a fast-paced and ambitious environment, collaborating with people across different functional areas, and thriving during crisis times, we encourage you to apply and join us!
Description
Building and maintaining Palladium emulation environments, including compile flows, netlist preparation, memory modeling, and clock/reset configurations.
System-level debug and root cause analysis of complex hardware issues on the emulation platform.
IP-level debug and validation, working closely with IP owners to isolate and resolve design issues.
Development and implementation of automation aids, flows, and scripts to improve Palladium build efficiency, debug turnaround, and platform utilization.
Performance profiling and optimization of emulation models to maximize execution speed.
Collaboration with multi-disciplinary groups to make sure emulation deliverables are on schedule and support critical program milestones.
Responsibilities
Own and maintain Palladium emulation build flows for SoC and subsystem-level models
Drive debug and triage of emulation model issues, working with RTL designers and verification engineers
Support system-level hardware validation efforts and hardware integration
Develop reusable debug methodologies and collateral to accelerate issue resolution
Optimize emulation model performance through compile tuning, partitioning strategies, and platform configuration
Thoroughly document flows, debug procedures, and best practices
Collaborate with cross-functional teams to define emulation requirements and support prototype hardware validation
If you enjoy a fast-paced and ambitious environment, collaborating with people across different functional areas, and thriving during crisis times, we encourage you to apply and join us!
Description
Building and maintaining Palladium emulation environments, including compile flows, netlist preparation, memory modeling, and clock/reset configurations.
System-level debug and root cause analysis of complex hardware issues on the emulation platform.
IP-level debug and validation, working closely with IP owners to isolate and resolve design issues.
Development and implementation of automation aids, flows, and scripts to improve Palladium build efficiency, debug turnaround, and platform utilization.
Performance profiling and optimization of emulation models to maximize execution speed.
Collaboration with multi-disciplinary groups to make sure emulation deliverables are on schedule and support critical program milestones.
Responsibilities
Own and maintain Palladium emulation build flows for SoC and subsystem-level models
Drive debug and triage of emulation model issues, working with RTL designers and verification engineers
Support system-level hardware validation efforts and hardware integration
Develop reusable debug methodologies and collateral to accelerate issue resolution
Optimize emulation model performance through compile tuning, partitioning strategies, and platform configuration
Thoroughly document flows, debug procedures, and best practices
Collaborate with cross-functional teams to define emulation requirements and support prototype hardware validation
Requirements:
Proven experience with Cadence Palladium (or equivalent emulation platforms such as Synopsys ZeBu), including build flows, compile optimization, and platform bring-up
Strong debugging skills with experience in system-level and IP-level debug on emulation platforms
Experience with emulation compile flows, including synthesis for emulation, memory compilation, clock modeling, and I/O abstraction
Proficiency in debug tools and methodologies (waveform analysis, signal probing, assertion-based debug, transactors)
Solid understanding of RTL design concepts, SoC architectures, ARM-based subsystems, and standard bus protocols (AXI, AHB, APB)
Experience developing and maintaining automation scripts (Python, Tcl, Perl, Shell) to streamline emulation workflows
Strong analytical and problem-solving skills with ability to debug complex system-level issues
Experience with Wireless SoC applications (Wi-Fi, Bluetooth, cellular) – strongly preferred
Excellent communication and collaboration skills to work effectively across functional teams
Experience with version control systems (Git, Perforce) and CI/CD integration for emulation flows
Proven experience with Cadence Palladium (or equivalent emulation platforms such as Synopsys ZeBu), including build flows, compile optimization, and platform bring-up
Strong debugging skills with experience in system-level and IP-level debug on emulation platforms
Experience with emulation compile flows, including synthesis for emulation, memory compilation, clock modeling, and I/O abstraction
Proficiency in debug tools and methodologies (waveform analysis, signal probing, assertion-based debug, transactors)
Solid understanding of RTL design concepts, SoC architectures, ARM-based subsystems, and standard bus protocols (AXI, AHB, APB)
Experience developing and maintaining automation scripts (Python, Tcl, Perl, Shell) to streamline emulation workflows
Strong analytical and problem-solving skills with ability to debug complex system-level issues
Experience with Wireless SoC applications (Wi-Fi, Bluetooth, cellular) – strongly preferred
Excellent communication and collaboration skills to work effectively across functional teams
Experience with version control systems (Git, Perforce) and CI/CD integration for emulation flows
This position is open to all candidates.
