As a verification engineer, you will make a difference by influencing the verification strategy and methodology, taking ownership of complex work packages and driving them to success.
Required Skills and Experience:
Meticulous attention to detail, ensuring high-quality verification that minimizes bug escapes.
Shown experience in block-level verification using UVM or similar methodologies.
Strong knowledge of coverage driven verification for complex designs.
Proficient in specifying, creating, and debugging SystemVerilog/UVM constrained-random testbenches.
Skilled in planning verification tasks and producing realistic effort and time estimates.
Experience in working with requirements definition and management.
Formal verification experience.
Proficiency in developing C/C++ models of a microarchitecture.
Familiarity with Arm architecture and AMBA bus protocols.
Experience with CI platforms and version control tools.
Practical knowledge of machine learning and neural networks.






















