we are looking for a Wafer-Scale System: Computation (LLM) and Communication (NoC) Co-Design.
Responsibilities:
Conduct cutting-edge research on the co-design of communication and computation for wafer-scale systems. On the communication side, the work focuses on architecting Networks-on-Chip, providing scalable, high-bandwidth, and ultra-low-latency interconnects that efficiently span multiple dies and support fine-grained data movement. On the computation side, the research emphasizes optimizing and mapping training and inference workloads to fully exploit wafer-scale resources, improving performance, scalability, and energy efficiency through intelligent task placement and scheduling.
Investigate various aspects of system design, including:
Network-on-Chip design, further including Topology exploration, routing algorithms, and protocol/flow-control design to support high-throughput collective communication, low-latency synchronization, and efficient model/data parallelism
Expressing and Mapping LLM Parallelism to Wafer-Scale System that simplify LLM parallelism (e.g., tensor, pipeline, and data parallelism) and efficiently map training and inference workloads onto wafer-scale system
Responsibilities:
Conduct cutting-edge research on the co-design of communication and computation for wafer-scale systems. On the communication side, the work focuses on architecting Networks-on-Chip, providing scalable, high-bandwidth, and ultra-low-latency interconnects that efficiently span multiple dies and support fine-grained data movement. On the computation side, the research emphasizes optimizing and mapping training and inference workloads to fully exploit wafer-scale resources, improving performance, scalability, and energy efficiency through intelligent task placement and scheduling.
Investigate various aspects of system design, including:
Network-on-Chip design, further including Topology exploration, routing algorithms, and protocol/flow-control design to support high-throughput collective communication, low-latency synchronization, and efficient model/data parallelism
Expressing and Mapping LLM Parallelism to Wafer-Scale System that simplify LLM parallelism (e.g., tensor, pipeline, and data parallelism) and efficiently map training and inference workloads onto wafer-scale system
Requirements:
Master in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field.
Background in interconnection networks and computer architecture is a must.
Demonstrated research expertise in one or both of the following areas:
Network-on-Chip (NoC) architecture, including routing, flow control, topologies, and performance modeling
LLM parallel execution and co-design, including workload decomposition, communication-computation overlap, and mapping to high-performance interconnects
Excellent analytical, problem-solving, and system-level thinking skills.
Excellent programming skills with hands-on experience in simulator modeling, development and simulator-based evaluation.
Strong verbal and written communication skills, and the ability to work both independently and collaboratively in a cross-disciplinary team.
Master in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field.
Background in interconnection networks and computer architecture is a must.
Demonstrated research expertise in one or both of the following areas:
Network-on-Chip (NoC) architecture, including routing, flow control, topologies, and performance modeling
LLM parallel execution and co-design, including workload decomposition, communication-computation overlap, and mapping to high-performance interconnects
Excellent analytical, problem-solving, and system-level thinking skills.
Excellent programming skills with hands-on experience in simulator modeling, development and simulator-based evaluation.
Strong verbal and written communication skills, and the ability to work both independently and collaboratively in a cross-disciplinary team.
This position is open to all candidates.
