Required Staff RTL IP/Component Design Engineer, Cloud
About the job
In this role, you will contribute in all phases of complex application-specific integrated circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and etc. to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next-generation of our platforms, we make product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Define the block level design document such as interface protocol, block diagram, transaction flow and pipeline, etc.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, and VHDL), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Support synthesis, timing/power closure, and Field Programmable Gate Array (FPGA)/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
About the job
In this role, you will contribute in all phases of complex application-specific integrated circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and etc. to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next-generation of our platforms, we make product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Define the block level design document such as interface protocol, block diagram, transaction flow and pipeline, etc.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, and VHDL), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Support synthesis, timing/power closure, and Field Programmable Gate Array (FPGA)/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).
Experience in ASIC development with Verilog/SystemVerilog, VHDL or Chisel.
Experience with System on a Chip (SoC) development cycles.
Preferred qualifications:
Proficiency with a scripting language (e.g., Python or Perl).
Knowledge of high performance and low power design techniques.
Knowledge of assertion-based formal verification.
Knowledge of FPGA and emulation platforms.
Knowledge of SOC architecture.
Knowledge in one of these areas: arithmetic units, bus architectures, processor design, accelerators or memory hierarchies.
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).
Experience in ASIC development with Verilog/SystemVerilog, VHDL or Chisel.
Experience with System on a Chip (SoC) development cycles.
Preferred qualifications:
Proficiency with a scripting language (e.g., Python or Perl).
Knowledge of high performance and low power design techniques.
Knowledge of assertion-based formal verification.
Knowledge of FPGA and emulation platforms.
Knowledge of SOC architecture.
Knowledge in one of these areas: arithmetic units, bus architectures, processor design, accelerators or memory hierarchies.
This position is open to all candidates.
