What you'll be doing:
Lead the end-to-end execution, tracking, and convergence of chip-level CDC and RDC for complex SoCs across all IPs and partitions.
Plan and orchestrate CDC/RDC signoff: define methodology, scopes, run plans, constraints, and acceptance criteria.
Run and maintain CDC/RDC flows and rule decks, including multi-mode, multi-clock, and hierarchical signoff.
Triage violations efficiently: root-cause to RTL, constraints, tool setup, or IP models; prioritize and drive fixes to closure with owners.
Verify reset architecture and RDC robustness (reset domain intent, release sequencing, glitch detection, fanout).
Author and review CDC/RDC constraints, waivers, and justifications; ensure auditability and signoff quality.
Automate runs, report parsing, dashboards, and KPIs for closure tracking using scripting and data tooling.
Partner with RTL, DV, DFT, STA, PD, and Architecture to align fixes, manage ECOs, and protect CDC/RDC quality during late design changes.
Define and enforce signoff gates; communicate progress and risks with clear metrics and issue tracking.
Continually improve methodology and training to prevent recurring CDC/RDC issues and accelerate convergence.
What we need to see:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering.
7+ years of actual design experience in chip design.
Strong RTL proficiency in SystemVerilog for reading/debugging designs and implementing CDC/RDC-safe structures.
Experience with constraints and timing intent (SDC) and their interaction with CDC/RDC.
Hands-on expertise with industry CDC/RDC tools (e.g., SpyGlass, Questa CDC, Real Intent) and lint/formal where relevant.
Proficiency in at least one scripting languages like Python, bash, Perl, TCL.
Great teammate.
Way to stand out from the crowd:
Passion for quality. Experience with delivery to physical design and other customers.
