Required Senior Verification Engineer (FPGA)
Were seeking passionate professionals who thrive in a fast-paced, creative, and collaborative environment – those who want to be part of the next generation of airspace security innovation.
Join us and help make the world a safer place.
Work with the worlds leading cyber-takeover counter-drone technology provider and shape the future of safe airspace.
Lead the functional sign-off for complex FPGA designs by architecting scalable, reusable UVM-based verification environments.
You will build the essential infrastructure that empowers FPGA designers to efficiently and accurately verify their own modules.
Key Responsibilities:
Architecture: Build and maintain advanced simulation environments from scratch using UVM and SystemVerilog.
Strategy & Coverage: Develop comprehensive verification plans to drive the team toward 100% functional and code coverage closure.
CI/CD & Automation: Architect robust automated regression testing environments and integrate them into CI/CD pipelines (e.g., Jenkins).
Tool Expertise: Serve as the internal authority for EDA tools (like Questa) and manage high-performance simulations.
Debugging: Perform deep root-cause analysis on complex failing tests and hardware logic.
Were seeking passionate professionals who thrive in a fast-paced, creative, and collaborative environment – those who want to be part of the next generation of airspace security innovation.
Join us and help make the world a safer place.
Work with the worlds leading cyber-takeover counter-drone technology provider and shape the future of safe airspace.
Lead the functional sign-off for complex FPGA designs by architecting scalable, reusable UVM-based verification environments.
You will build the essential infrastructure that empowers FPGA designers to efficiently and accurately verify their own modules.
Key Responsibilities:
Architecture: Build and maintain advanced simulation environments from scratch using UVM and SystemVerilog.
Strategy & Coverage: Develop comprehensive verification plans to drive the team toward 100% functional and code coverage closure.
CI/CD & Automation: Architect robust automated regression testing environments and integrate them into CI/CD pipelines (e.g., Jenkins).
Tool Expertise: Serve as the internal authority for EDA tools (like Questa) and manage high-performance simulations.
Debugging: Perform deep root-cause analysis on complex failing tests and hardware logic.
Requirements:
Minimum Qualifications:
7+ years of professional functional verification experience for FPGA or ASIC designs.
At least 5 years of proven expertise in building a complete Full-Chip UVM test environment from scratch.
Strong command of SystemVerilog and Verilog.
Extensive experience with EDA tools (specifically Questa) and complex hardware debugging.
FPGA Knowledge: Prior experience or background with FPGAs is a significant advantage.
Preferred Qualifications:
Proficiency in Matlab for DPI or bit-exact modeling.
Scripting experience (Python/Tcl/Bash) for building automated CI/CD regression flows.
Familiarity with Questa tools is preferred.
Minimum Qualifications:
7+ years of professional functional verification experience for FPGA or ASIC designs.
At least 5 years of proven expertise in building a complete Full-Chip UVM test environment from scratch.
Strong command of SystemVerilog and Verilog.
Extensive experience with EDA tools (specifically Questa) and complex hardware debugging.
FPGA Knowledge: Prior experience or background with FPGAs is a significant advantage.
Preferred Qualifications:
Proficiency in Matlab for DPI or bit-exact modeling.
Scripting experience (Python/Tcl/Bash) for building automated CI/CD regression flows.
Familiarity with Questa tools is preferred.
This position is open to all candidates.
