This is an opportunity for an excellent silicon engineer to take meaningful technical ownership in a dynamic, agile, and highly collaborative environment. You will work on advanced subsystem design spanning microarchitecture, RTL implementation, integration, and design quality, with close collaboration across architecture, verification, firmware, system engineering, and physical design teams.
The role focuses on complex security-oriented silicon subsystems. We are looking for someone who combines strong design fundamentals with curiosity, ownership, and the motivation to learn and apply modern techniques – including AI-assisted workflows – to improve silicon development productivity and quality.
Responsibilities
Own and drive microarchitecture and RTL design for complex silicon blocks and subsystems, translating architecture and system requirements into clean, efficient, and high-quality hardware implementations.
Collaborate closely with verification, firmware, system engineering, architecture, and physical design partners to define interfaces, debug complex issues, manage technical risks, and deliver robust silicon solutions.
Contribute to subsystem integration, design reviews, quality checks, synthesis readiness, timing considerations, and design handoff flows.
Explore and apply modern silicon development workflows, including AI-assisted techniques for design productivity, debug, documentation, and quality improvements.
Act as a technical leader within the team by mentoring others, raising the engineering bar, and helping drive execution in a fast-moving environment.
B.Sc. or higher in Electrical Engineering, Computer Engineering, or a related technical field.
Proven experience and technical excellence in RTL design for complex IPs, subsystems, or SoCs.
Proven hands-on experience with Verilog/SystemVerilog, microarchitecture definition, RTL implementation, design reviews, and design quality practices.
Preferred Qualifications:
Experience applying AI-assisted techniques to improve silicon design productivity, debug, documentation, automation, or workflow efficiency.
Experience with security-oriented silicon subsystems, including crypto engines, memory protection, secure boot, trusted execution, or related hardware security domains.
Experience working across key parts of the silicon development lifecycle, including verification collaboration, integration, synthesis readiness, timing considerations, and design closure.
Experience with low-power design, performance optimization, clock/reset architecture, CDC/RDC, lint, synthesis, or timing closure.
Experience acting as a technical leader, design owner, or mentor for other engineers.
Strong problem-solving skills, ownership mindset, and ability to drive technical work independently while collaborating effectively across disciplines.
High motivation, curiosity, and willingness to learn new domains, tools, and methodologies.
