we are seeking a highly motivated Power Integrity Engineer to join our Hardware Engineering team. In this role, you will be responsible for defining, analyzing, simulating, and validating power delivery networks (PDNs) for next-generation networking platforms supporting high-performance ASICs, advanced SerDes interfaces, optical modules, and AI-scale networking systems.
You will work closely with hardware architects, PCB designers, ASIC teams, signal integrity engineers, mechanical engineers, and manufacturing partners to ensure robust power delivery, optimal system performance, and successful product deployment.
Responsibilities:
Lead Power Integrity (PI) activities throughout the hardware development lifecycle, from architecture through production.
Define and optimize board-level and package-level Power Delivery Networks (PDNs) for high-current networking ASICs and supporting devices.
Perform pre-layout and post-layout PI simulations using industry-standard tools.
Establish target impedance requirements and validate compliance across all power rails.
Analyze DC voltage drop, AC impedance, transient response, and power distribution performance.
Collaborate with PCB layout engineers to optimize stackups, plane structures, decoupling strategies, and power routing.
Work closely with Signal Integrity engineers to ensure SI/PI co-optimization of high-speed interfaces.
Develop power integrity design guidelines and best practices for next-generation networking products.
Support schematic reviews, layout reviews, and design sign-off activities.
Perform laboratory measurements and correlation using oscilloscopes, VNAs, power analyzers, current probes, and related equipment.
Investigate and resolve PI-related issues during board bring-up, validation, and production.
Collaborate with ASIC, FPGA, memory, optics, and power component vendors to optimize overall system performance.
Drive continuous improvement of PI methodologies, simulation flows, and validation processes.
You will work closely with hardware architects, PCB designers, ASIC teams, signal integrity engineers, mechanical engineers, and manufacturing partners to ensure robust power delivery, optimal system performance, and successful product deployment.
Responsibilities:
Lead Power Integrity (PI) activities throughout the hardware development lifecycle, from architecture through production.
Define and optimize board-level and package-level Power Delivery Networks (PDNs) for high-current networking ASICs and supporting devices.
Perform pre-layout and post-layout PI simulations using industry-standard tools.
Establish target impedance requirements and validate compliance across all power rails.
Analyze DC voltage drop, AC impedance, transient response, and power distribution performance.
Collaborate with PCB layout engineers to optimize stackups, plane structures, decoupling strategies, and power routing.
Work closely with Signal Integrity engineers to ensure SI/PI co-optimization of high-speed interfaces.
Develop power integrity design guidelines and best practices for next-generation networking products.
Support schematic reviews, layout reviews, and design sign-off activities.
Perform laboratory measurements and correlation using oscilloscopes, VNAs, power analyzers, current probes, and related equipment.
Investigate and resolve PI-related issues during board bring-up, validation, and production.
Collaborate with ASIC, FPGA, memory, optics, and power component vendors to optimize overall system performance.
Drive continuous improvement of PI methodologies, simulation flows, and validation processes.
Requirements:
B.Sc. or M.Sc. in Electrical Engineering.
5+ years of experience in Power Integrity, Hardware Design, or related disciplines.
Strong understanding of power delivery networks, decoupling methodologies, and target impedance concepts.
Hands-on experience with PI simulation tools such as:
Cadence Sigrity PowerSI / OptimizePI
Ansys SIwave
Ansys HFSS
PowerDC or equivalent
Experience designing high-layer-count PCBs for networking, telecom, server, or data-center products.
Knowledge of high-speed digital systems and interaction between Signal Integrity and Power Integrity.
Experience with multi-phase voltage regulators, power sequencing, and power management architectures.
Strong understanding of PCB materials, stackups, and manufacturing constraints.
Experience performing lab validation and correlation measurements.
Excellent problem-solving, communication, and teamwork skills.
Preferred Qualifications:
Experience with high-performance networking ASICs and switch silicon.
Familiarity with 112G/224G/448G PAM4 SerDes technologies.
Experience with Ethernet systems ranging from 400G to 1.6T and above.
Understanding of package-level PI and advanced packaging technologies.
Familiarity with optical networking platforms and co-packaged optics.
Experience with thermal and mechanical effects on PDN performance.
Knowledge of EMI/EMC considerations in high-density networking systems.
Experience working with ODMs, CMs, and global manufacturing partners.
B.Sc. or M.Sc. in Electrical Engineering.
5+ years of experience in Power Integrity, Hardware Design, or related disciplines.
Strong understanding of power delivery networks, decoupling methodologies, and target impedance concepts.
Hands-on experience with PI simulation tools such as:
Cadence Sigrity PowerSI / OptimizePI
Ansys SIwave
Ansys HFSS
PowerDC or equivalent
Experience designing high-layer-count PCBs for networking, telecom, server, or data-center products.
Knowledge of high-speed digital systems and interaction between Signal Integrity and Power Integrity.
Experience with multi-phase voltage regulators, power sequencing, and power management architectures.
Strong understanding of PCB materials, stackups, and manufacturing constraints.
Experience performing lab validation and correlation measurements.
Excellent problem-solving, communication, and teamwork skills.
Preferred Qualifications:
Experience with high-performance networking ASICs and switch silicon.
Familiarity with 112G/224G/448G PAM4 SerDes technologies.
Experience with Ethernet systems ranging from 400G to 1.6T and above.
Understanding of package-level PI and advanced packaging technologies.
Familiarity with optical networking platforms and co-packaged optics.
Experience with thermal and mechanical effects on PDN performance.
Knowledge of EMI/EMC considerations in high-density networking systems.
Experience working with ODMs, CMs, and global manufacturing partners.
This position is open to all candidates.
