What you'll be doing:
Thoroughly understand our networking solutions across all performance related aspects.
Develop a C++ simulation model to define and evaluate architectural options for our next generation of networking products.
Understand different trade-offs related to solving performance bottlenecks.
Collaborate and lead technical solutions within architecture, uarch, hardware and software teams.
Analyze and model the communication patterns of key DL, GAI, inference, and training applications.
Explore innovative ideas to improve and optimize our chip systems performance.
What we need to see:
BSc/MSc in Computer Science, Electrical Engineering, from a known university.
Experience in Chip deign projects, understanding the challenges of HW uarch impelementations.
Excellent verbal and written communication skills, orchestrating cross teams activities.
High level of ownership and the ability to drive solutions and initiatives.
Proficiency in C++ and Python.
5+ years of hands-on experience.
Strong debug skills.
Ways to stand out from the crowd:
Master's degree in Electrical Engineering, Computer Science or related technical field.
Demonstrated ability to innovate and lead new technologies leading to product impact.
Experience with NVLink/Ethernet/IB technologies.
