Our innovative packet processors power some of the most advanced data centers in the world and are designed into tier-1 vendor platforms. With state-of-the-art technology, a strong track record of industry recognition, and multiple award-winning achievements, we continuously push the boundaries of performance and scalability.
Our group is involved across the entire development lifecycle – from early research and architectural definition to silicon production – working on both research initiatives and production-grade products.
What will you be doing?
Lead research, evaluation, and architectural definition of next-generation chips – from requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet Switches.
Design the system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate closely with design, verification, and modeling teams to ensure architectural intent is fully realized.
Work cross-functionally with other architecture teams to shape cohesive system solutions.
Explore and evaluate new technologies and innovative approaches for future products.
Requirements
BSc / MSc / PhD in Electrical Engineering, Computer Engineering, or a related field.
7+ years of experience in VLSI / ASIC design, chip architecture, or micro-architecture of complex blocks.
Strong background in high-speed networking systems such as:
o Ethernet Switches
o NPUs
o NICs
o Traffic Managers
o Fabric Switches
o High-performance processors
Skills
What Were Looking For
Excellent written and verbal communication skills in English.
Strong collaboration skills and the ability to work effectively across teams and disciplines.
Independent, self-driven, and capable of deep technical ownership.
Passion for innovation and cutting-edge technology.
Highly motivated with a proactive mindset.
