As a Senior Chip Design Engineer on the Nitro team, you will take full end-to-end ownership of one or more critical IP blocks within the product, guiding them from micro-architecture definition through RTL design, debug, synthesis, timing closure, and final sign-off before tape-out. Your work will ship in silicon that powers AWS at global scale.
You'll partner closely with the Verification and Emulation teams to shape test plans, review coverage, and close gaps early in the design cycle. Beyond your own IP, you'll collaborate across disciplines with Product Definition, Software, Physical Design, and Verification teams to deliver a fully integrated, production-ready chip.
Key job responsibilities
* Full ownership of one or more IPs within the product:
Micro-architecture definition.
RTL coding and debug.
Synthesis and timing closure.
Sign-off before tape-out.
* Supporting the Verification and Emulation teams: Test plan development, coverage review.
* Ensuring the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical Design.
Basic Qualifications
– 6+ years of experience in chip design.
– Hands-on experience in micro-architecture and RTL design (Verilog / System Verilog).
– Scripting expertise in C*, Perl, Python, or TCL.
– BSc in Computer/Electrical Engineering.
– Strong communication and collaboration skills.
– Strong leadership skills and ability to own complex units.
Preferred Qualifications
– Strong knowledge of protocols (AXI, CHI, DDR, Networking, PCIe).
– Experience with Network-on-Chip (NOC) architecture.
– knowledge with coherent and non-coherent fabric design.
– Comprehensive SoC development cycle expertise (Synthesis, STA, CDC, Lint).
– Knowledge of Design Automation tools and techniques.
– Advanced degree in related technical field.
