Our Logic Design team builds the on-chip monitoring IP at the heart of our product – digital blocks that ship inside some of the most advanced chips in the industry. Were growing the team and looking for a Logic Design Engineer to take ownership of that logic, working alongside circuit, verification, physical design, EDA, and AE engineers. A strong fit if you enjoy hard digital design problems in a collaborative, technically demanding environment.
Responsibilities
Define and implement digital logic micro-architecture – in plain English, diagrams, and SystemVerilog.
Verify design quality against industry standards using static analysis tools (Lint, CDC, RDC).
Work with Circuit Engineers to turn low-level circuit designs into the well-behaved, insightful agents at the core of the proteanTecs solution.
Work with Verification Engineers to simulate and debug the digital logic.
Work with Physical Design Engineers to ensure correct implementation of our special circuits.
Requirements:
B.Sc. or M.Sc. in Electrical or Computer Engineering.
5+ years as a VLSI front-end engineer (logic/ASIC/chip design) or in a similar domain.
Strong background in RTL design, handoff methodologies, and signoff tools (Lint, CDC, RDC).
Close familiarity with python, Git, Unix-like environment – an advantage.
Experience with low-power design techniques (clock gating, power domains, DVFS) – an advantage.
Knowledge of DFT design and flows – an advantage.
Personal skills:
Self-driven – takes a task from definition to signoff, pulling in whoever is needed along the way.
Detail-oriented, with a sharp eye for issues others miss.
A clear communicator who can convey technical tradeoffs to cross-functional teams.
Curious about new design techniques and methodologies.
