In this role, you will be responsible for developing, validating, and supporting digital test content for NVIDIAs advanced Network Silicon ICs (Switches, NICs, SmartNICs). You will work closely with DFT, design, and test engineering teams to ensure high-quality and scalable test content from wafer to final product.
What you'll be doing:
Develop ATPG, LBIST, and MBIST content based on DFT architecture.
Run validation flows (simulation/emulation/silicon), analyze failures, and debug pattern issues.
Collaborate with DFT teams to ensure alignment between test logic and content implementation.
Support test program bring-up and pattern integration on production testers.
Continuously improve coverage, pattern quality, and pattern generation efficiency.
Work with product and test engineering to support yield improvement and debug activities.
What we need to see:
B.Sc. in Electrical Engineering.
Strong understanding of scan, ATPG, BIST (MBIST/LBIST), and DFT concepts.
3 years of experience in digital test content development or related roles.
Scripting skills (Python/TCL/Perl) – an advantage.
Strong analytical and debug skills, independent and detail-oriented.
Ways to stand out from the crowd:
Familiarity with ATE test environments (e.g., UltraFlex).
Experience with silicon validation and failure analysis.
Knowledge in STA, RTL simulation, or gate-level netlist analysis.
