Responsibilities
Execute full-chip and block-level physical design tasks including floorplanning, placement, clock tree synthesis, routing, and physical verification.
Develop and optimize the digital backend flow.
Drive timing closure, power optimization, and physical verification (LVS/DRC/ERC).
Collaborate with front-end designers to address timing and logical/physical interface issues.
Support tapeout preparation and final signoff processes.
Masters or PhD degree in Electrical/Electronic Engineering or a related field.
4+ years experience in digital IC backend implementation.
Proficiency with backend EDA tools, particularly Cadence Innovus and Genus.
Strong understanding of place & route (P&R), static timing analysis (STA), DRC/LVS verification, IR drop, and electromigration (EM) analysis.
Experience with advanced technology nodes (22nm or below preferred).
Skilled in Tcl scripting for automation of backend flows.
Experience in hierarchical or full-chip implementation is preferred.
Language: English at a proficient level. French is a plus.
