Develop and maintain internal EDA tools and frameworks for RTL assembly and connectivity checking.
Implement efficient algorithms for hierarchical RTL construction, module binding, and interface consistency across complex SoCs.
Build intelligent connectivity, visualization, and debug utilities.
Collaborate with front-end design, DFT, and integration teams to align methodologies and define tool requirements.
Drive automation and performance improvements, including runtime optimization and scalability across large designs.
Support adoption, documentation, and user training for internal design teams.
Implement efficient algorithms for hierarchical RTL construction, module binding, and interface consistency across complex SoCs.
Build intelligent connectivity, visualization, and debug utilities.
Collaborate with front-end design, DFT, and integration teams to align methodologies and define tool requirements.
Drive automation and performance improvements, including runtime optimization and scalability across large designs.
Support adoption, documentation, and user training for internal design teams.
Requirements:
Minimum Qualifications
BSc/MSc in Electrical Engineering, Computer Engineering, or Computer Science.
5+ years of experience in FE design or integration.
Experience as team lead – advantage.
Minimum Qualifications
BSc/MSc in Electrical Engineering, Computer Engineering, or Computer Science.
5+ years of experience in FE design or integration.
Experience as team lead – advantage.
Preferred Qualifications
Good programming skills in Python and C/C++.
Solid understanding of RTL design (Verilog/SystemVerilog) and SoC integration concepts.
This position is open to all candidates.
