The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Evaluate, analyze, implement, and integrate SRAMs, other memories (such as multiport register files), and custom circuits. Drive proper IP integration and margins with the physical design team.
Partner with foundries and IP providers, as well as internal technology, physical design, and architecture teams, to optimize products for PPA, schedule, and reliability in advanced CMOS nodes.
Drive and support test chip design, execution, and validation of critical circuit IPs.
Design and build custom circuits at the transistor and gate levels to support physical design and power-performance-area optimization.
Drive development of a leading edge technology platform for custom, high performance ASICs and SoCs, from design through manufacturing, packaging, and test.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Evaluate, analyze, implement, and integrate SRAMs, other memories (such as multiport register files), and custom circuits. Drive proper IP integration and margins with the physical design team.
Partner with foundries and IP providers, as well as internal technology, physical design, and architecture teams, to optimize products for PPA, schedule, and reliability in advanced CMOS nodes.
Drive and support test chip design, execution, and validation of critical circuit IPs.
Design and build custom circuits at the transistor and gate levels to support physical design and power-performance-area optimization.
Drive development of a leading edge technology platform for custom, high performance ASICs and SoCs, from design through manufacturing, packaging, and test.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience in Circuit Design, Physical Design (RTL-to-GDS), or Technology Development, including advanced nodes (e.g., 7nm or below).
Experience with custom circuit/IP and physical design, including Place and Route (PNR) and Static Timing Analysis (STA).
Experience in scripting and automation using Tcl and Python (or Perl).
Experience with SPICE and transistor level design in advanced nodes.
Experience in CMOS device physics, finfet/GAA/nanosheet architectures, and layout parasitics.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience working with major foundry technology files (PDKs), standard cell libraries, metal stacks, and other features.
Understanding of characterization and verification of standard cells/SRAMs/register files, including knowledge of power, noise, variation, and IR analysis.
Understanding of collaterals for front end and back end design teams.
Excellent track record of delivering optimized custom circuits/memories/IPs and PNR blocks for product tapeout.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience in Circuit Design, Physical Design (RTL-to-GDS), or Technology Development, including advanced nodes (e.g., 7nm or below).
Experience with custom circuit/IP and physical design, including Place and Route (PNR) and Static Timing Analysis (STA).
Experience in scripting and automation using Tcl and Python (or Perl).
Experience with SPICE and transistor level design in advanced nodes.
Experience in CMOS device physics, finfet/GAA/nanosheet architectures, and layout parasitics.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience working with major foundry technology files (PDKs), standard cell libraries, metal stacks, and other features.
Understanding of characterization and verification of standard cells/SRAMs/register files, including knowledge of power, noise, variation, and IR analysis.
Understanding of collaterals for front end and back end design teams.
Excellent track record of delivering optimized custom circuits/memories/IPs and PNR blocks for product tapeout.
This position is open to all candidates.
