Your Impact:
Write and review micro-architecture specifications.
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements.
Contribute to full chip integration, timing methodology, and analysis.
Collaborate with verification engineers to resolve bugs and achieve coverage closure.
Work with the physical design team to close timing and PnR issues.
Support design methodology evolution and best practices.
Perform debug, root-cause analysis, and post-silicon validation in the lab.
Write and review micro-architecture specifications.
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements.
Contribute to full chip integration, timing methodology, and analysis.
Collaborate with verification engineers to resolve bugs and achieve coverage closure.
Work with the physical design team to close timing and PnR issues.
Support design methodology evolution and best practices.
Perform debug, root-cause analysis, and post-silicon validation in the lab.
Requirements:
Minimum Qualifications:
B.Sc./M.Sc. in Electrical Engineering from a top university.
RTL design experience.
Familiarity with UVM and functional verification methodologies.
Minimum Qualifications:
B.Sc./M.Sc. in Electrical Engineering from a top university.
RTL design experience.
Familiarity with UVM and functional verification methodologies.
Preferred Qualifications:
Experience with MATLAB simulations and bit-exact modeling environments.
Familiarity with mixed-signal systems and environments.
Knowledge and hands-on experience with Clock Domain Crossing (CDC).
This position is open to all candidates.
