Responsibilities
" Verification environments creation, using SystemVerilog and UVM.
" Units and chip level TEST plan creation
" Implementation of TEST plans, TEST writing and debug
" Functional and code coverage of the design and TEST plan
" Simulation hardware accelerators (Synopsys Zebu) responsibility
" Leading a team of Verification engineers
Requirements:
" B.Sc. or higher in Electrical Engineering or computer engineering.
"
" At least 5 years of experience in Verification and/or IC design.
" Outstanding technical expertise in the successful completion of multiple VLSI implementation and verification projects.
" Programming languages: C, Verilog, SystemVerilog, scripting, are a must.
" Experience with, and thorough understanding of up-to-date RTL design, simulation and verification methodology, tools and languages.
" Strong communication and interpersonal skills to work closely with a variety of individual contributors and managers from different functional groups.
" Experience as a team leader is a must
" B.Sc. or higher in Electrical Engineering or computer engineering.
"
" At least 5 years of experience in Verification and/or IC design.
" Outstanding technical expertise in the successful completion of multiple VLSI implementation and verification projects.
" Programming languages: C, Verilog, SystemVerilog, scripting, are a must.
" Experience with, and thorough understanding of up-to-date RTL design, simulation and verification methodology, tools and languages.
" Strong communication and interpersonal skills to work closely with a variety of individual contributors and managers from different functional groups.
" Experience as a team leader is a must
This position is open to all candidates.
