" Verification at SOC level
" Understanding all flows and mechanisms in the chip
" Ramp up and infrastructure build of full-chip environment, integration of cluster environments to full-chip
" Focal point of all tests written for full-chip level by team
" Work closely with emulation and SW teams
" Location: Caesarea / Tel Aviv
" Experience in full-chip verification, writing C tests on CPUs
" Experience with UVM integration
_________________________________________
-Own tasks of ASIC verification
-Develop TEST environments in system Verilog
-Create verification plans
-Debug ASIC designs
-Integrate unknit level environment for full chip
-Participate in design reviews
-Collaborate with your peers in the architecture, design and SW teams
" Understanding all flows and mechanisms in the chip
" Ramp up and infrastructure build of full-chip environment, integration of cluster environments to full-chip
" Focal point of all tests written for full-chip level by team
" Work closely with emulation and SW teams
" Location: Caesarea / Tel Aviv
" Experience in full-chip verification, writing C tests on CPUs
" Experience with UVM integration
_________________________________________
-Own tasks of ASIC verification
-Develop TEST environments in system Verilog
-Create verification plans
-Debug ASIC designs
-Integrate unknit level environment for full chip
-Participate in design reviews
-Collaborate with your peers in the architecture, design and SW teams
Requirements:
3+ years of experience in ASIC Verification
-Experience in functional verification on block level
-Knowledge of building verification plan
-Good communication skills
-Fast learner
-Advantage: Specman, system Verilog, E, UVM
3+ years of experience in ASIC Verification
-Experience in functional verification on block level
-Knowledge of building verification plan
-Good communication skills
-Fast learner
-Advantage: Specman, system Verilog, E, UVM
This position is open to all candidates.
