In this visible role, you will be responsible for defining DV methodologies, test-bench infrastructure and project execution for the next generation MSP (Memory Signal Processing) IPs to enable state of the art storage solutions for Apple products line.
Description
You will develop verification test plans, test benches, tools and infrastructure, protocol monitors and agents, and coverage driven stimulus in UVM.
Apply advanced techniques to achieve verification with the highest quality, productivity, and time-to-market.
Apply deep system level understanding to find system architecture bugs, verifying the DUT at multiple levels – from block level to the entire IP and subsystem, with additional emphasis on power (NLP) and performance.
You will work closely with the design, architecture, software, system and validation teams from the early stages of IP definition, to ensure timely delivery of quality designs.
Involvement with Post Silicon Validation and other verification teams.
Description
You will develop verification test plans, test benches, tools and infrastructure, protocol monitors and agents, and coverage driven stimulus in UVM.
Apply advanced techniques to achieve verification with the highest quality, productivity, and time-to-market.
Apply deep system level understanding to find system architecture bugs, verifying the DUT at multiple levels – from block level to the entire IP and subsystem, with additional emphasis on power (NLP) and performance.
You will work closely with the design, architecture, software, system and validation teams from the early stages of IP definition, to ensure timely delivery of quality designs.
Involvement with Post Silicon Validation and other verification teams.
Requirements:
5+ years of experience in SoC or IP verification
Advanced knowledge of SoC architecture/design, in-depth knowledge of verification flows and broad system view
Expected to have a deep understanding and shown experience in advanced verification processes, including coverage driven and formal methods
Extensive experience with SystemVerilog and UVM
Experience with verification infrastructure development
Scripting and programming experience using several of the following: Perl, Python, Verilog, SystemVerilog, C, C++, and TCL
5+ years of experience in SoC or IP verification
Advanced knowledge of SoC architecture/design, in-depth knowledge of verification flows and broad system view
Expected to have a deep understanding and shown experience in advanced verification processes, including coverage driven and formal methods
Extensive experience with SystemVerilog and UVM
Experience with verification infrastructure development
Scripting and programming experience using several of the following: Perl, Python, Verilog, SystemVerilog, C, C++, and TCL
This position is open to all candidates.
