You will work on pioneering technology that powers the future of the Internet.
You will be part of a global team working on the newest generation of us, which will be integrated across the entire portfolio of our devices.
You will collaborate with worldwide distributed R&D centers, gaining exposure to some of the most talented engineers in the networking industry. We look for people who love technology and engineering-people who thrive on innovation, continuous learning, and challenging whats possible.
Your Impact:
Design, implement, and test a state-of-the-art optimizing compiler for us.
Evaluate and optimize code performance, including debugging, code generation improvements, and pipeline analysis.
Develop, optimize, and enhance the compiler backend to fully leverage cutting-edge hardware capabilities.
Solve complex resource management challenges across hardware pipelines.
Design and implement new P4 language features that empower network application developers.
Build and maintain the compiler toolchain for custom networking applications.
Contribute to libraries, analysis tools, and supporting infrastructure.
Collaborate with cross-functional hardware and software teams.
Work closely with ASIC engineers on next-generation IC design, influencing hardware through compiler insights prior to tape-out.
Minimum Qualifications:
3+ years of experience developing or maintaining large-scale software projects.
Bachelors or Masters degree in Computer Science or related field.
Strong skills in modern C++, software design, and debugging.
Fluent in written and spoken English.
Preferred Qualifications:
Experience with compiler infrastructures (LLVM, MLIR).
Knowledge of compiler optimization (theoretical or practical).
Experience with Python, ANTLR, SWIG, or similar tools.
Background in hardware/software co-design.
Understanding of performance analysis and profiling techniques.
Excellent analytical and problem-solving abilities.
Motivated to learn, proactive, and comfortable working autonomously.
