Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. As a worker, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The our company's System-On-Chip (SOC) group is looking for a top physical design engineer with a curiosity about SOC design optimization, physical integration, chip build and assembly and verification. You should have real passion for methodologies and clock distribution solutions that enable SOC creation in the most optimized way. In this position, you will get the opportunity to build complex networking chips and directly contact unit-level owners, Physical Design, CAD, Package Design, Software, DFT and other teams.
What you'll be doing:
Designing and implementing SOC level clock requirements
Daily work involves aspects of chip level design, including partitioning, CDC, trial synthesis, design quality checks
Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, resolve design quality issues.
The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The our company's System-On-Chip (SOC) group is looking for a top physical design engineer with a curiosity about SOC design optimization, physical integration, chip build and assembly and verification. You should have real passion for methodologies and clock distribution solutions that enable SOC creation in the most optimized way. In this position, you will get the opportunity to build complex networking chips and directly contact unit-level owners, Physical Design, CAD, Package Design, Software, DFT and other teams.
What you'll be doing:
Designing and implementing SOC level clock requirements
Daily work involves aspects of chip level design, including partitioning, CDC, trial synthesis, design quality checks
Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, resolve design quality issues.
Requirements:
B.SC. in Electrical Engineering/Computer Engineering.
3+ years of confirmed experience in chip design
Shown hands on physical design skills in clock distribution in tight multi power and timing/layout constrained products.
Proficiency in at least one common scripting languages like perl, python, bash, Tcl.
Phenomenal teammate.
Ways to stand out from the crowd:
Passion for quality. Experience with delivery back to RTL, to physical design, and other customers.
B.SC. in Electrical Engineering/Computer Engineering.
3+ years of confirmed experience in chip design
Shown hands on physical design skills in clock distribution in tight multi power and timing/layout constrained products.
Proficiency in at least one common scripting languages like perl, python, bash, Tcl.
Phenomenal teammate.
Ways to stand out from the crowd:
Passion for quality. Experience with delivery back to RTL, to physical design, and other customers.
This position is open to all candidates.
