We are looking for a Senior Verification engineer to be a significant part in developing a complex and innovative SOC chip in a start-up company.
Taking full ownership of entire domain, defining the verification strategy, writing, and executing verification plan in system Verilog UVM.
About Us:
VLSI group is responsible for the development of our next generation SOC for AI Compute.
The development starts from product definition through architecture, design, verification and up to implementation.
The complex SOC is a high-performance device running AI compute for vision and audio processing, with technologies from multi-disciplines.
Taking full ownership of entire domain, defining the verification strategy, writing, and executing verification plan in system Verilog UVM.
About Us:
VLSI group is responsible for the development of our next generation SOC for AI Compute.
The development starts from product definition through architecture, design, verification and up to implementation.
The complex SOC is a high-performance device running AI compute for vision and audio processing, with technologies from multi-disciplines.
Requirements:
5+ years of experience as a Verification engineer.
B.Sc./M.Sc. in Electrical/Computer Engineering from a leading university.
Strong knowledge of system Verilog and UVM methodology.
Experience in pre-silicon functional unit level/cluster/full chip verification.
Experience in verification of packet processing/Ethernet/RDMA/InfiniBand
Familiarity with SOC architecture, CPU subsystems, and multi-core designs.
Advantages
Knowledge of formal verification and emulation/FPGA prototyping.
Exposure to AI/Networking workloads and performance validation.
5+ years of experience as a Verification engineer.
B.Sc./M.Sc. in Electrical/Computer Engineering from a leading university.
Strong knowledge of system Verilog and UVM methodology.
Experience in pre-silicon functional unit level/cluster/full chip verification.
Experience in verification of packet processing/Ethernet/RDMA/InfiniBand
Familiarity with SOC architecture, CPU subsystems, and multi-core designs.
Advantages
Knowledge of formal verification and emulation/FPGA prototyping.
Exposure to AI/Networking workloads and performance validation.
This position is open to all candidates.
