Required Senior Verification engineer SoC group
Responsibilities:
Take on a significant role in a small team developing the System-On-Chip of our cutting-edge 5G IoT and AI products. in this role, youll investigate, invent, develop, innovate, and improve challenging verification environments, from block-level to chip-level. Youll work with sophisticated verification methodologies implementing System-On-Chip flows, collaborate with the design team, and support SW and production teams. Youll also research cutting-edge industry technology and standards in various fields such as communications, processors, and interconnect.
Responsibilities:
Take on a significant role in a small team developing the System-On-Chip of our cutting-edge 5G IoT and AI products. in this role, youll investigate, invent, develop, innovate, and improve challenging verification environments, from block-level to chip-level. Youll work with sophisticated verification methodologies implementing System-On-Chip flows, collaborate with the design team, and support SW and production teams. Youll also research cutting-edge industry technology and standards in various fields such as communications, processors, and interconnect.
Requirements:
BSc in electrical or computer engineering/computer science from an established university
At least 6 years experience in the verification flow of complex designs from test plan definition to coverage closure
Understanding of high-level system flows and constraints
Team player with a proactive attitude
Independent thinker, curious, and motivated
Experience in Specman and/or System Verilog must
Nice to have:
Experience in UVM
Background in System-On-Chip flows and on-chip interconnect protocols.
BSc in electrical or computer engineering/computer science from an established university
At least 6 years experience in the verification flow of complex designs from test plan definition to coverage closure
Understanding of high-level system flows and constraints
Team player with a proactive attitude
Independent thinker, curious, and motivated
Experience in Specman and/or System Verilog must
Nice to have:
Experience in UVM
Background in System-On-Chip flows and on-chip interconnect protocols.
This position is open to all candidates.
