We are looking for a Senior Verification Engineer to be a significant part in developing a complex and innovative SoC chip in a start-up company.
Taking full ownership of entire domain, defining the verification strategy, writing and executing test plan in system Verilog UVM.
Requirements:
5+ years of experience as a Verification Engineer.
B.Sc./M.Sc. degree in electrical/computer engineering from a leading university
Experience in pre-silicon functional unit level verification.
Experience in System Verilog UVM.
Experience in verification of complex SoC and designs.
Experience with AMBA protocols and NOC subsystem is an advantage
Experience with CPU subsystem is an advantage
Experience with NOC subsystem is an advantage
Experience in leading block/cluster verification from scratch is an advantage
5+ years of experience as a Verification Engineer.
B.Sc./M.Sc. degree in electrical/computer engineering from a leading university
Experience in pre-silicon functional unit level verification.
Experience in System Verilog UVM.
Experience in verification of complex SoC and designs.
Experience with AMBA protocols and NOC subsystem is an advantage
Experience with CPU subsystem is an advantage
Experience with NOC subsystem is an advantage
Experience in leading block/cluster verification from scratch is an advantage
This position is open to all candidates.
