we are looking for a Senior Verification Engineer.
Your Impact
Develop advanced verification environments using SystemVerilog and UVM
Write, run, and debug testbenches to ensure complete functional coverage
Drive pre-silicon and in-lab debug activities to resolve complex issues
Collaborate with RTL, architecture, and physical design teams to achieve design closure
Support methodology development, scripting, and automation to enhance productivity
Contribute to the success, powering the next generation of Internet infrastructure
Your Impact
Develop advanced verification environments using SystemVerilog and UVM
Write, run, and debug testbenches to ensure complete functional coverage
Drive pre-silicon and in-lab debug activities to resolve complex issues
Collaborate with RTL, architecture, and physical design teams to achieve design closure
Support methodology development, scripting, and automation to enhance productivity
Contribute to the success, powering the next generation of Internet infrastructure
Requirements:
6+ years of experience in digital logic design verification
Advanced knowledge of SystemVerilog and UVM
Strong debug skills both pre-silicon and in-lab
Preferred Qualifications
Scripting skills (Python, Perl, TCL, or shell)
Experience with system-level integration (AMBA, PCIe, SPI, I2C, JTAG, CPU)
Basic software knowledge (driver-level)
Basic design knowledge and familiarity with CDC concepts
6+ years of experience in digital logic design verification
Advanced knowledge of SystemVerilog and UVM
Strong debug skills both pre-silicon and in-lab
Preferred Qualifications
Scripting skills (Python, Perl, TCL, or shell)
Experience with system-level integration (AMBA, PCIe, SPI, I2C, JTAG, CPU)
Basic software knowledge (driver-level)
Basic design knowledge and familiarity with CDC concepts
This position is open to all candidates.
