Required Senior SoC verification engineer
About this position:
As a Senior SoC Verification Engineer, you will play a pivotal role in our VLSI group, contributing to the development of cutting-edge AI chips.
If you are motivated and skilled in VLSI and excited about AI, we want to meet you!
Responsibilities:
Collaborate closely with verification teams, architecture, and design teams to develop and execute a comprehensive verification strategy for various blocks and flows within our System-on-chip (SoC) and Neural Network (NN) processor, ensuring high-quality standards and prompt execution.
Actively participate in large-scale integration efforts and contribute to maintaining and enhancing the UVM-based verification environment, ensuring it aligns with and enhances group methodologies for verifying complex SoC designs efficiently.
Analyze and optimize system flows to verify a fully functional design meeting logical specifications and performance criteria, ensuring efficient and effective verification processes.
Experience with scripting languages such as Python or Perl.
About this position:
As a Senior SoC Verification Engineer, you will play a pivotal role in our VLSI group, contributing to the development of cutting-edge AI chips.
If you are motivated and skilled in VLSI and excited about AI, we want to meet you!
Responsibilities:
Collaborate closely with verification teams, architecture, and design teams to develop and execute a comprehensive verification strategy for various blocks and flows within our System-on-chip (SoC) and Neural Network (NN) processor, ensuring high-quality standards and prompt execution.
Actively participate in large-scale integration efforts and contribute to maintaining and enhancing the UVM-based verification environment, ensuring it aligns with and enhances group methodologies for verifying complex SoC designs efficiently.
Analyze and optimize system flows to verify a fully functional design meeting logical specifications and performance criteria, ensuring efficient and effective verification processes.
Experience with scripting languages such as Python or Perl.
Requirements:
Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field from a reputable university.
Minimum of 8 years of experience in ASIC design or verification.
Proficiency in SystemVerilog and proven experience with UVM verification methodology.
Familiarity with large-scale SoC verification processes.
Excellent communication skills and ability to collaborate effectively in a team environment.
Advantages
Experience with emulation.
Strong advantage: Experience with ARM subsystems.
Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field from a reputable university.
Minimum of 8 years of experience in ASIC design or verification.
Proficiency in SystemVerilog and proven experience with UVM verification methodology.
Familiarity with large-scale SoC verification processes.
Excellent communication skills and ability to collaborate effectively in a team environment.
Advantages
Experience with emulation.
Strong advantage: Experience with ARM subsystems.
This position is open to all candidates.
