What you'll be doing:
You will be in charge of developing physical design, synthesis, STA and Logic eq methodologies for implementation of networking chips and SOCs.
Work closely with block owners. full Chip STA engineers and project managers to assure high quality and timely convergence.
Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.
Additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.
What we need to see:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).
At least 5 years of experience
Should be a power user of synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Innovus/Tempus) with 5+ years of experience.
Proficiency using Python, Perl, Tcl, Make scripting.
Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes.
Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power required and implementing them through ECOs is required.
Knowledge in process variation effect modeling and experience in design convergence taking into account variations.
Successful track record of delivering designs to production is necessary.
Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.
Great teammate, ownership, self-learning skills, and ability to work autonomously.
Ways to stand out from the crowd:
Experience in methodology definition / flow owner of synthesis / Place and Route/ STA steps is an advantage.
