we are looking for outstanding Chip Design Verification Engineers to join our Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
Come and take a significant part in designing and verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
What you will be doing:
Join Tel Aviv group, working in a combined design and verification team which develops Phy Layer IP within the Networking silicon.
Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.
Come and take a significant part in designing and verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
What you will be doing:
Join Tel Aviv group, working in a combined design and verification team which develops Phy Layer IP within the Networking silicon.
Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.
Requirements:
B.Sc in Electrical Engineering or equivalent experience.
5+ years of validated experience in RTL Frontend ASIC Design or Verification (Chip Design). Less experienced engineers with outstanding academic records will also be considered.
Strong debugging, problem-solving and analytical skills.
A great teammate with strong communication and interpersonal skills.
Ways to stand out from the crowd:
Knowledge in Specman.
Knowledge in Verilog.
B.Sc in Electrical Engineering or equivalent experience.
5+ years of validated experience in RTL Frontend ASIC Design or Verification (Chip Design). Less experienced engineers with outstanding academic records will also be considered.
Strong debugging, problem-solving and analytical skills.
A great teammate with strong communication and interpersonal skills.
Ways to stand out from the crowd:
Knowledge in Specman.
Knowledge in Verilog.
This position is open to all candidates.
