our copmpany's Networking Clock design team is looking for experienced top notch ASIC design engineer to work on next generation of our company Networking chips. We're looking for profound and multi-disciplinary background in Clock design domains to lead Clocks Micro-Architecture activities. This role requires working with multiple teams as Architecture, IP, Physical design, Timing and Post-Si teams. Complexity of clocking scheme has grown substantially over recent chip generations with increased focus on performance, power and quality. Modern Clocking design needs to balance high frequency clocks with power, DFx, noise, circuit and physical design constraints.
What you will be doing:
Working on next generation of Networking Switch, NIC and SoC products.
Micro architect and design next generation clock topologies and modules.
ASIC Clock scheme definition.
Improve Power, Performance, and Area (PPA) of state-of-the-art company chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.
Collaborate with Physical design and timing team to evaluate Clocking concerns and come up with solutions for supporting high speed Clocking.
Understand physical aspects of the chip and develop enhanced clock distribution techniques.
Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.
Support Post-Si debug, characterization and productization activities.
What you will be doing:
Working on next generation of Networking Switch, NIC and SoC products.
Micro architect and design next generation clock topologies and modules.
ASIC Clock scheme definition.
Improve Power, Performance, and Area (PPA) of state-of-the-art company chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.
Collaborate with Physical design and timing team to evaluate Clocking concerns and come up with solutions for supporting high speed Clocking.
Understand physical aspects of the chip and develop enhanced clock distribution techniques.
Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.
Support Post-Si debug, characterization and productization activities.
Requirements:
BSc or MSc degrees in EE or equivalent experience from known universities.
At least 5+ years of work experience in RTL design, Gate-Level and Circuit design optimization.
Deep understanding of logic optimization techniques and PPA trade-offs.
Excellent interpersonal skills and ability to collaborate with multiple teams.
Excellent problem solving and debugging skills.
Ways to stand out from the crowd:
Prior experience in RTL design (Verilog), verification and synthesis.
Clock IPs profound knowledge: PLL, DLL, Compensator.
Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a bonus. Prior experience in implementing on-chip clocking networks.
BSc or MSc degrees in EE or equivalent experience from known universities.
At least 5+ years of work experience in RTL design, Gate-Level and Circuit design optimization.
Deep understanding of logic optimization techniques and PPA trade-offs.
Excellent interpersonal skills and ability to collaborate with multiple teams.
Excellent problem solving and debugging skills.
Ways to stand out from the crowd:
Prior experience in RTL design (Verilog), verification and synthesis.
Clock IPs profound knowledge: PLL, DLL, Compensator.
Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a bonus. Prior experience in implementing on-chip clocking networks.
This position is open to all candidates.
