Were looking for a Physical Verification Expert to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Leading Physical Verification activities & methodologies for a brand new SoC, from definition to Tape Out.
Physical verification owner, defining Physical Verification methodologies & activities for Full Chip, Sub System & Block Level.
ESD planning & implementation; IO Pad, Bump, RDL planning.
Block Ownership from RTL to GDS.
Working with engineers to identify and overcome roadblocks and obstacles.
What will your job look like:
Leading Physical Verification activities & methodologies for a brand new SoC, from definition to Tape Out.
Physical verification owner, defining Physical Verification methodologies & activities for Full Chip, Sub System & Block Level.
ESD planning & implementation; IO Pad, Bump, RDL planning.
Block Ownership from RTL to GDS.
Working with engineers to identify and overcome roadblocks and obstacles.
Requirements:
BSc/MSc in Electrical Engineering/Computer Science.
8 years of experience in VLSI backend (RTL2GDS).
5 years of experience in Full Chip Integration & verification on complex SoCs.
Physical Verification Expert (DRC/LVS/PERC).
Expert knowledge in floor planning, integration & signoff methodologies for hierarchical designs.
Experience with IO Pad, Bump & ESD planning.
Experience in technically leading complex backend activities, preferably of complete SoC’s.
Expert knowledge of the entire backend design flow from RTL to TO. (Synthesis, FP, PnR , CTS , STA, EM/IR, Chip Integration & Physical Signoff).
BSc/MSc in Electrical Engineering/Computer Science.
8 years of experience in VLSI backend (RTL2GDS).
5 years of experience in Full Chip Integration & verification on complex SoCs.
Physical Verification Expert (DRC/LVS/PERC).
Expert knowledge in floor planning, integration & signoff methodologies for hierarchical designs.
Experience with IO Pad, Bump & ESD planning.
Experience in technically leading complex backend activities, preferably of complete SoC’s.
Expert knowledge of the entire backend design flow from RTL to TO. (Synthesis, FP, PnR , CTS , STA, EM/IR, Chip Integration & Physical Signoff).
This position is open to all candidates.
