our company's EyeC VLSI team – a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block or IP owner from RTL to GDS with horizontal domain ownership.
Collaboration with front-end and architecture teams to address issues, define design methodologies and improve QoR & convergence.
End to End ownership from Synthesis, DFT insertion, Floor Planning , Place & Route till signoff.
Signoff on all domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.
Exploratio of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new technologies tools & features and to bring innovation with significant RoI.
Technical support and mentoring the engineers in the team.
What will your job look like:
Hands-on physical design block or IP owner from RTL to GDS with horizontal domain ownership.
Collaboration with front-end and architecture teams to address issues, define design methodologies and improve QoR & convergence.
End to End ownership from Synthesis, DFT insertion, Floor Planning , Place & Route till signoff.
Signoff on all domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.
Exploratio of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new technologies tools & features and to bring innovation with significant RoI.
Technical support and mentoring the engineers in the team.
Requirements:
BSc or MSc degree in Electrical Engineering or Computer Engineering.
8+ years of experience in the Physical Design field.
Experience with high-speed interfaces (DDR/PCIE) – an advantage.
Experience with advanced nodes (5nm and below) – an advantage.
Building or maintaining implementation tools and flow – an advantage.
Experience in scripting languages like Tcl/Python/Perl/TCSH.
Team player with excellent communication skills, customer orientation, and a can-do attitude.
BSc or MSc degree in Electrical Engineering or Computer Engineering.
8+ years of experience in the Physical Design field.
Experience with high-speed interfaces (DDR/PCIE) – an advantage.
Experience with advanced nodes (5nm and below) – an advantage.
Building or maintaining implementation tools and flow – an advantage.
Experience in scripting languages like Tcl/Python/Perl/TCSH.
Team player with excellent communication skills, customer orientation, and a can-do attitude.
This position is open to all candidates.
