our company's EyeC VLSI team – a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design CAD Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Participate in the development of flows & methodologies from Synthesis , Place& Route & all signoff flows.
Plan & execute flow releases, coordinate & track development tasks.
Exploration of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new tools features and methodologies to bring innovation with significant RoI.
Hands-on physical design block ownership end to end, from Synthesis floor planning, Place & Route with target to achieve best PPA.
Signoff on all domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.
Serve as the technical lead while mentoring and guiding team members.
What will your job look like:
Participate in the development of flows & methodologies from Synthesis , Place& Route & all signoff flows.
Plan & execute flow releases, coordinate & track development tasks.
Exploration of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new tools features and methodologies to bring innovation with significant RoI.
Hands-on physical design block ownership end to end, from Synthesis floor planning, Place & Route with target to achieve best PPA.
Signoff on all domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.
Serve as the technical lead while mentoring and guiding team members.
Requirements:
BSc or MSc degree in Electrical Engineering or Computer Engineering.
7+ years of experience in the Physical Design field.
Expert knowledge of the entire backend design flow from RTL to TO (Synthesis, Floorplanning, PnR , CTS , STA, EM/IR, Chip Integration).
Experience in technically leading horizontal backend activities.
Experience with flow development, exploration & tuning.
Experience with Synthesis, P&R & signoff closure on all domains.
Experience in scripting languages like Tcl/Python/Perl/TCSH & version controltools.
Experience with advanced nodes (5nm and below) – an advantage.
Team player with excellent communication skills, customer orientation, and a can-do attitude.
BSc or MSc degree in Electrical Engineering or Computer Engineering.
7+ years of experience in the Physical Design field.
Expert knowledge of the entire backend design flow from RTL to TO (Synthesis, Floorplanning, PnR , CTS , STA, EM/IR, Chip Integration).
Experience in technically leading horizontal backend activities.
Experience with flow development, exploration & tuning.
Experience with Synthesis, P&R & signoff closure on all domains.
Experience in scripting languages like Tcl/Python/Perl/TCSH & version controltools.
Experience with advanced nodes (5nm and below) – an advantage.
Team player with excellent communication skills, customer orientation, and a can-do attitude.
This position is open to all candidates.
