What you’ll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) – synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.
What we need to see:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.
3+ years of experience in physical design.
Proven experience in RTL2GDS flows and methodologies.
Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
Deep understanding of all aspects of Physical construction and Integration.
Deep understanding of Physical Design Verification methodology LVS/DRC.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
Great teammate.
