We are looking for an experienced engineer to develop multiple IPs for Apple SoCs (in Storage, Computer Vision and RISC-V CPU domains). In this Role you will get to handle micro-architecture definitions, RTL coding, block level simulations and synthesis.
Role expectations include working with partner design teams, physical design, verification, platform architecture and software teams to define the IPs micro architecture, implement the required HW and integrate it into multiple sub-systems in Apple SoCs. In addition, you will synthesize the digital design to the latest process nodes and participate in the implementation process. If you are looking for a challenging technical role with a broad system view in a complex, control-oriented IPs, this could be a great opportunity for you.
Role expectations include working with partner design teams, physical design, verification, platform architecture and software teams to define the IPs micro architecture, implement the required HW and integrate it into multiple sub-systems in Apple SoCs. In addition, you will synthesize the digital design to the latest process nodes and participate in the implementation process. If you are looking for a challenging technical role with a broad system view in a complex, control-oriented IPs, this could be a great opportunity for you.
Requirements:
Key Qualifications:
3+ year experience in VLSI design of Processor Cores/SoC.
Familiar with advanced design practices (Clock/Voltage domain crossing and Low Power Design).
Strong Verilog/System Verilog skills
Familiar with CPU/ARM instruction set standard an advantage
Familiar with the various backend tools (synthesis and STA) an advantage.
Experience with scripting and programming experience using several of the following: Perl, C, Python, and TCL.
Familiar with verification methodologies an advantage.
Key Qualifications:
3+ year experience in VLSI design of Processor Cores/SoC.
Familiar with advanced design practices (Clock/Voltage domain crossing and Low Power Design).
Strong Verilog/System Verilog skills
Familiar with CPU/ARM instruction set standard an advantage
Familiar with the various backend tools (synthesis and STA) an advantage.
Experience with scripting and programming experience using several of the following: Perl, C, Python, and TCL.
Familiar with verification methodologies an advantage.
This position is open to all candidates.
