In this highly visible role, you will be working with the elite CPU and SOC teams which powers products that are exceptionally efficient and exceptionally performant. You will be at the center of a chip design effort interfacing with all disciplines spread across multiple geographies, with a critical impact on getting functional products to millions of customers quickly.
The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
Play a critical role in end-to-end verification of memory subsystem by developing an in-depth understanding of cache coherence protocols and functioning of various units in CPU/SOC that are relevant to memory subsystem verification. These units include Load-Store unit, different levels of caches, bus interface units, memory controller, etc.
Develop verification environment which can be used in both simulation and emulation.
Develop synthesizable transactors and test benches and support verification hooks for verifying memory subsystem functionality and CPU/SOC features.
Develop unit level stimulus as well as full chip assembly or C programs to verify memory subsystem functionality.
Develop verification IPs that can be utilized by our teams worldwide
Work closely with the CPU/SOC RTL spread across US and Israel to understand the specification in detail for developing verification strategy taking system level considerations into account.
Develop coverage monitors and accomplish coverage goals for closure of the design.
Develop abstract end-to-end checks to verify CPU-SOC memory subsystem interaction and coherence protocols.
Key Qualifications:
5+ years of processor verification experience.
knowledge of digital logic design, CPU and SOC architecture/micro-architecture and memory subsystem.
Strong programming C/C++, Verilog, Scripting, software optimization, and performance improvement skills.
Experience in unit and full chip level test benches.
Experience in developing testplans, assertions, and developing stimulus.
Experience with emulation and developing synthesizable transactors is a plus.
Understanding of cache organization, basic cache coherence protocols and key CPU structures.
Education & Experience:
BS in Computer Engineering, Electrical Engineering.
