Google's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets Google's standards of quality and reliability. The AI and Infrastructure team is redefining whats possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Design, develop, and maintain CAD tools and scripts to automate and streamline design tasks, verification processes, and data analysis.
Administer and optimize the front-end compute environment, ensuring reliability, performance, and scalability.
Provide technical support and training to Design and Verification teams on the use of CAD tools, scripts, and the compute environment.
Identify opportunities to enhance front-end development workflows, implement improvements, and document best practices.
Work closely with design, verification, and CAD teams to understand their needs, gather requirements, and deliver effective solutions.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Design, develop, and maintain CAD tools and scripts to automate and streamline design tasks, verification processes, and data analysis.
Administer and optimize the front-end compute environment, ensuring reliability, performance, and scalability.
Provide technical support and training to Design and Verification teams on the use of CAD tools, scripts, and the compute environment.
Identify opportunities to enhance front-end development workflows, implement improvements, and document best practices.
Work closely with design, verification, and CAD teams to understand their needs, gather requirements, and deliver effective solutions.
Requirements:
Minimum qualifications:
Bachelors degree or equivalent practical experience.
3 years of experience in coding or scripting languages (e.g., Python, TCL).
Experience with front-end design, verification, integration teams on tools development, maintenance, or support.
Preferred qualifications:
Experience in CPU or SoC design, debug, and verification flows.
Experience working with RTL teams and design integration methodologies that improve team productivity and velocity.
Experience with delivering chip design infrastructure or methodology including multi-HDL model builds and CI/CD systems.
Minimum qualifications:
Bachelors degree or equivalent practical experience.
3 years of experience in coding or scripting languages (e.g., Python, TCL).
Experience with front-end design, verification, integration teams on tools development, maintenance, or support.
Preferred qualifications:
Experience in CPU or SoC design, debug, and verification flows.
Experience working with RTL teams and design integration methodologies that improve team productivity and velocity.
Experience with delivering chip design infrastructure or methodology including multi-HDL model builds and CI/CD systems.
This position is open to all candidates.
