What you will be doing:
Join Tel Aviv group, working on designing and verifying the new generation of high-speed ports.
Design and verification for chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area, and performance
Daily work might involve any or all aspects of chip development: Verification, Design, and Micro-Architecture.
Work closely with Firmware and other groups around the globe.
What we need to see:
B.SC./ M.SC. in Electrical Engineering/Communication Engineering/Computer Engineering.
3+ years of validated experience in RTL Frontend ASIC Design or Verification (Chip Design). Less experienced engineers with high university grades will also be considered.
High Level of English.
Ways to stand out from the crowd:
Background in Specman.
Knowledge in Verilog.
