What you will be doing:
Join Beer-Sheva group, working on designing/verification in the fields of encryption accelerators.
Design and verification for chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area and performance.
Daily work will involve verification and might involve any or all aspects of chip development including design and micro-architecture.
Work closely with firmware and other groups around the globe.
Work mode: Hybrid – 2 days from office, 3 days from home.
What we need to see:
B.SC./M.SC. or equivalent experience in Electrical Engineering/Communication Engineering/Computer Engineering.
2+ years of validated experience in RTL Frontend ASIC Verification or Design (Chip Design).
High Level of English.
Ways to stand out from the crowd:
4+ years experience in RTL Frontend ASIC.
Knowledge in Specman.
Knowledge in Verilog.
