We are looking for experience engineers to develop, maintain, and enhance existing sophisticated software systems for regression-testing silicon designs in software simulation, find and report defects in our chip designs, and thus ensure tape-out world-class silicon.
As a member of our CAD team, you will work closely with EDA vendors to incorporate new capabilities of their commercial tools and to resolve problems
Your experience and insight, your skill at diagnosing the root cause of complex problems, and your ability to guide engineers who come to you with problems will be important contributions to an extended CAD team that comprehensively supports verification and design engineering efforts.
Description
You will Develop, maintain, and enhance an existing system for regressing RTL.
Role involves debugging vendor tool problems.
Interacting with Verification teams to help solve their problems.
Implement new functionality to solve emerging problems or to optimize already existing methods.
As a member of our CAD team, you will work closely with EDA vendors to incorporate new capabilities of their commercial tools and to resolve problems
Your experience and insight, your skill at diagnosing the root cause of complex problems, and your ability to guide engineers who come to you with problems will be important contributions to an extended CAD team that comprehensively supports verification and design engineering efforts.
Description
You will Develop, maintain, and enhance an existing system for regressing RTL.
Role involves debugging vendor tool problems.
Interacting with Verification teams to help solve their problems.
Implement new functionality to solve emerging problems or to optimize already existing methods.
Requirements:
5+ years of experience in Verilog and System Verilog
Experienced with Synopsys VCS, NC-Verilog, or Models’ – A must
Strong scripting abilities in PERL are needed; TCL or Python is a plus
Good communications skills are required and prior customer support experience is a plus
Experience writing or maintaining the script or Makefile that builds the simulation Program from RTL is a plus. Familiarity with Verdi and/or DVE is considered a plus
Knowledge at C and C++ is a plus
Education & Experience
BSc/ MSc in Electrical Engineering or Computer Science.
5+ years of experience in Verilog and System Verilog
Experienced with Synopsys VCS, NC-Verilog, or Models’ – A must
Strong scripting abilities in PERL are needed; TCL or Python is a plus
Good communications skills are required and prior customer support experience is a plus
Experience writing or maintaining the script or Makefile that builds the simulation Program from RTL is a plus. Familiarity with Verdi and/or DVE is considered a plus
Knowledge at C and C++ is a plus
Education & Experience
BSc/ MSc in Electrical Engineering or Computer Science.
This position is open to all candidates.
