We are looking for a FPGA Verification Engineer to join our team!
The company leads the market by adopting innovative technologies & providing top-notch development solutions, and now we are looking for you an FPGA Verification Engineer to join our growing team.
Job Description:
Design and implement verification plans for IP level, chip level, and board level environments
Develop RTL Test Benches in UVM or System Verilog
Develop self-checking test benches and unit tests for high speed digital systems
Develop Built-In-Test (BIT) and support of debug and system integration activities
Develop scripts using Tcl or Python for regression testing
Develop BFMs and IP for reuse in multiple projects.
The company leads the market by adopting innovative technologies & providing top-notch development solutions, and now we are looking for you an FPGA Verification Engineer to join our growing team.
Job Description:
Design and implement verification plans for IP level, chip level, and board level environments
Develop RTL Test Benches in UVM or System Verilog
Develop self-checking test benches and unit tests for high speed digital systems
Develop Built-In-Test (BIT) and support of debug and system integration activities
Develop scripts using Tcl or Python for regression testing
Develop BFMs and IP for reuse in multiple projects.
Requirements:
BS/MS Electrical Engineering or Computer Engineering or equivalent
3 6 years of IP design verification know-how
Expertise in constrained random testing, assertion based verification, clock domain crossing verification, and code coverage
Expertise in UVM and OVM is a must
FPGA implementation and debug experience.
Expertise with Xilinx and FPGAs and SoCs, including FPGA tool suites such as Xilinx Vivado
Expertise with AXI, I2C, PCIe, Ethernet, DSP, DDR2/3 is a plus
Expertise to develop requirements flow down system/subsystem/box/board levels is a plus
Expertise with Mentor Questa Simulator and System Verilog is a plus.
BS/MS Electrical Engineering or Computer Engineering or equivalent
3 6 years of IP design verification know-how
Expertise in constrained random testing, assertion based verification, clock domain crossing verification, and code coverage
Expertise in UVM and OVM is a must
FPGA implementation and debug experience.
Expertise with Xilinx and FPGAs and SoCs, including FPGA tool suites such as Xilinx Vivado
Expertise with AXI, I2C, PCIe, Ethernet, DSP, DDR2/3 is a plus
Expertise to develop requirements flow down system/subsystem/box/board levels is a plus
Expertise with Mentor Questa Simulator and System Verilog is a plus.
This position is open to all candidates.
