This is a highly visible position in CSG (Switching Group). We are looking for DFT engineer that wants to be part of the best implementation team, that performs a true RTL to production.
The DFT position involves ownership of testability, methodology and execution for assigned projects. The DFT engineer is responsible from RTL DFT insertion to final test program bring-up. The DFT engineers are implementing Boundary scan, MBIST, SCAN and SCAN compression, and more. They are generating all patterns and work on the chips final test programs.
The DFT position involves ownership of testability, methodology and execution for assigned projects. The DFT engineer is responsible from RTL DFT insertion to final test program bring-up. The DFT engineers are implementing Boundary scan, MBIST, SCAN and SCAN compression, and more. They are generating all patterns and work on the chips final test programs.
Requirements:
University Bs.C. Electrical Engineer
Minimum 4 years of experience
Knowledge is some or all of the following:
o SCAN and ATPG
o MBIST (Memory Build In Self-Test)
o LogicBist (Logic Build In Self-Test)
experience with some of the following:
o TETRAMAX / DFT compiler
o FAST SCAN / TESTKOMPRESS / Tessent
University Bs.C. Electrical Engineer
Minimum 4 years of experience
Knowledge is some or all of the following:
o SCAN and ATPG
o MBIST (Memory Build In Self-Test)
o LogicBist (Logic Build In Self-Test)
experience with some of the following:
o TETRAMAX / DFT compiler
o FAST SCAN / TESTKOMPRESS / Tessent
This position is open to all candidates.
