We are looking for talented verification engineer which have abilities to own complex tasks on one hand and on the other hand be a team player, working with different vertical team and disciplines.
In this role you will be:
Responsible for the Verification of Various IPs and top level designs.
Defining and implementing the Environment architecture.
Defining and implementing Test plans, coverage plans, etc
Requirements:
At least 3 years experience with Specman/system Verilog UVM based verification
Experience with Specman (Advantage)
Deep understanding of verification concepts and advanced methodologies
Experience developing verification environments from scratch
Background in Networking IPs , SOC
Understanding of verification and design practices
Verilog/System Verilog experience (Advantage)
Team player
Dynamic person
Hands on experience in ASIC verification
Fast Learner
Education: Leading university degree
At least 3 years experience with Specman/system Verilog UVM based verification
Experience with Specman (Advantage)
Deep understanding of verification concepts and advanced methodologies
Experience developing verification environments from scratch
Background in Networking IPs , SOC
Understanding of verification and design practices
Verilog/System Verilog experience (Advantage)
Team player
Dynamic person
Hands on experience in ASIC verification
Fast Learner
Education: Leading university degree
This position is open to all candidates.
