we are looking for talented engineers to help us develop a semiconductor platform based on a revolutionary architecture.
Take part in the development of cutting-edge products within a disruptive system architecture. You will have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment. AWS provides a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world.
Key job responsibilities:
Identifying and resolving design issues and debugging problems that may arise during the design process.
Broad influence inside and outside the team, playing a major role in leading the group and helping it grow.
Owning a domain in an SoC Fully responsible for its entire life cycle:
o High system view, based on major Architecture and Micro-architecture activities.
o Writing Register Transfer Level (RTL) code in hardware description languages such as Verilog or VHDL.
o Supporting the Verification and Emulation teams: Test plan, debug and review results.
o Ensuring that the final chip meets quality and reliability standards.
Collaborating with cross-functional teams, including Product Definition, Verification, Emulation, Software, and Silicon Integration.
Take part in the development of cutting-edge products within a disruptive system architecture. You will have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment. AWS provides a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world.
Key job responsibilities:
Identifying and resolving design issues and debugging problems that may arise during the design process.
Broad influence inside and outside the team, playing a major role in leading the group and helping it grow.
Owning a domain in an SoC Fully responsible for its entire life cycle:
o High system view, based on major Architecture and Micro-architecture activities.
o Writing Register Transfer Level (RTL) code in hardware description languages such as Verilog or VHDL.
o Supporting the Verification and Emulation teams: Test plan, debug and review results.
o Ensuring that the final chip meets quality and reliability standards.
Collaborating with cross-functional teams, including Product Definition, Verification, Emulation, Software, and Silicon Integration.
Requirements:
– B.Sc. in Computer Engineering/BS Computer science/Electrical Engineering
– 6+ years of experience in chip design
– Knowledge in Verilog/System Verilog
– Excellent communication and mentoring skills
– B.Sc. in Computer Engineering/BS Computer science/Electrical Engineering
– 6+ years of experience in chip design
– Knowledge in Verilog/System Verilog
– Excellent communication and mentoring skills
PREFERRED QUALIFICATIONS
– Experience as a first line manger or technical leader – advantage
– Experience in IP integration and/or full chip integration
– Experience with Fabrics and/or Processors
– Experience with protocols: PCIe, DDR, AXI, CHI
– Experience with BE tools
This position is open to all candidates.
