As a backend engineer, you will take a significant part of the full chip development flow, from RTL to GDS.
You will be responsible for Synthesis, Floor Planning, Place Route, STA, DFT architecture and more.
Herzliya
You will be responsible for Synthesis, Floor Planning, Place Route, STA, DFT architecture and more.
Herzliya
Requirements:
BSc. in Electrical/Communication/Computer engineering from a known university
3+ years of experience in ASIC backend design
Experience in STA Signoff – Must (Synopsys Primetime Advantage)
Familiarity with RTL to GDSII full flow implementation
Experience with IR drop – Advantage
Familiarity with advanced DFT flows tools – Advantage
Experience with small geometry process nodes
Familiarity with ICC2 tool Advantage
BSc. in Electrical/Communication/Computer engineering from a known university
3+ years of experience in ASIC backend design
Experience in STA Signoff – Must (Synopsys Primetime Advantage)
Familiarity with RTL to GDSII full flow implementation
Experience with IR drop – Advantage
Familiarity with advanced DFT flows tools – Advantage
Experience with small geometry process nodes
Familiarity with ICC2 tool Advantage
This position is open to all candidates.
