This is an RTL design and technical leadership role, not a circuit or transistor-level design role. Working from the clock architecture defined with the architecture and micro-architecture teams, you will lead its implementation in RTL, guide other engineers contributing to it, and drive it through to silicon in close partnership with Design Verification and Physical Design (backend). You will also interact regularly with CAD, Package Design, Software, and DFT teams.
What you'll be doing:
Acting as the technical lead for SOC clocks development – leading the implementation of the clocking logic from specification through tape-out and bring-up.
Working with the architecture and micro-architecture teams on the SOC clock and reset scheme: collecting clocking requirements from units across the chip, feeding back implementation and timing considerations, and translating the agreed scheme into a verifiable design.
Writing and reviewing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization.
Leading and mentoring other RTL engineers working on clocking: reviewing designs, setting coding and quality standards, and distributing work across the team.
Working hand-in-hand with the Physical Design (backend) team on clock tree implementation, SDC/timing constraints, partitioning, floorplan feedback, trial synthesis, and timing convergence.
Partnering with Design Verification on clocking testplans, functional and gate-level debug, and coverage closure.
Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows.
Representing clocking implementation in cross-functional design reviews with architecture, PD, DV, DFT, and CAD stakeholders.
What we need to see:
B.Sc./M.Sc. in Electrical Engineering or Computer Engineering.
8+ years of relevant experience in RTL/logic design, with multiple chips taken to tape-out.
Demonstrated technical leadership: leading a design area through implementation and tape-out, mentoring engineers, and coordinating across teams.
Expert hands-on RTL design skills in Verilog/SystemVerilog, with strong understanding of how RTL choices affect synthesis results, timing, area, and power.
Deep understanding of clocking and reset design: clock gating, clock muxing and dividers, glitchless clock switching, reset synchronization, and clock domain crossing.
Proficiency with design quality tooling – lint, CDC/RDC, formal verification, synthesis, and static timing analysis (STA) – including the ability to interpret results and drive fixes back into the RTL.
Experience taking a design from architecture and micro-architecture specification through verification, physical implementation, and silicon bring-up.
Great teammate with strong communication skills across micro-architecture, DV, backend, DFT, and software teams.
Ways to stand out from the crowd:
Prior hands-on experience with SOC-level clocking or reset logic on a taped-out chip.
Experience with PLL/clock generator integration and clock tree constraint development with backend teams.
Experience with high-speed networking, interconnect, or fabric designs.
Background with low-power design techniques (clock gating, DVFS, power domains, UPF).
Experience building automation for RTL integration, chip assembly, or design quality flows.
