As a member of Switch u/arch Team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement power analysis and reduction techniques for our next generation switches. Your contributions will help us gain early insight into energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements.
What You'll Be Doing:
Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.
Develop and share best practices for performing pre-silicon power analysis.
Perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny.
Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes.
Select and run a wide variety of workloads for power analysis.
Prototype new architectural features in Verilog and power analysis.
What We Need To See:
BSC or MS in Computer Engineering or Electrical Engineering.
5+ years of experience in chip design.
Good and interpersonal skills; much collaboration with design teams is expected.
Familiarity with Verilog and ASIC design or verification.
Desire to bring data-driven decision-making and analytics to improve our products.
Strong coding/automation skills, preferably in Python, Perl, and C++.
Ways to Stand Out From the Crowd:
Experience with Power Artist, PTPX (Prime Power RTL, RTL Architect).
Strong understanding of concepts of energy consumption, estimation, data movement and low power design.
